MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1175

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

14.8.78 DRAM Control Register 83 (HW_DRAM_CTL83)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
Reset
set
Bit
W
ODT_RD_MAP_
R
ODT_ALT_EN
OBSOLETE
Bit
W
31
0
R
RSVD1
RSVD4
31 25
31 28
27 24
Field
23 0
Field
CS3
RSVD4
24
30
0
15
0
29
0
HW_DRAM_CTL83
28
0
14
0
Always write zeroes to this field.
Enable use of non-DFI odt_alt signal.
Enables the use of the non-DFI compliant alternative ODT internal signal odt_alt, which is externally viewed
as the signal reserved0. This signal is only required if the user intends to use a CAS latency of 3 with ODT
support. The user will need to modify the dram_asic.v file for this support.
'b0 = ODT support with CAS latency 3 is not supported.
'b1 = ODT support with CAS latency 3 is supported but is not DFI compliant. This disables the interrupt bit
for ODT-with-CAS3 and disables the OVL error.
Always write zeroes to this field.
Always write zeroes to this field.
Determines which chip(s) will have termination when a read occurs on chip 3.
Sets up which (if any) chip(s) will have their ODT termination active while a read occurs on chip select X.
EMI will define this parameter at default for internal testing. The user is required is to change this setting to
meet system specifications.
Example: If the system consists of 4 chip selects and odt_rd_map_cs0 is set to 'b0010, then when CS0 is
performing a read, CS1 will have active ODT termination. And if odt_rd_map_cs0 was set to 'b1000, then
instead CS3 would be active.
27
0
ODT_RD_
MAP_CS3
26
0
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
12
0
23
0
HW_DRAM_CTL82 field descriptions
HW_DRAM_CTL83 field descriptions
800E_0000h base + 14Ch offset = 800E_014Ch
RSVD3
22
0
11
0
21
0
20
10
0
0
19
0
ODT_RD_
MAP_CS2
18
0
0
9
OBSOLETE[15:0]
17
0
16
0
0
8
15
0
Description
Description
RSVD2
14
0
7
0
13
0
0
12
6
0
Chapter 14 External Memory Interface (EMI)
11
0
ODT_RD_
MAP_CS1
5
0
10
0
0
9
4
0
0
8
0
7
0
RSVD1
3
0
6
0
5
0
2
0
4
3
0
ODT_RD_
MAP_CS0
0
1
0
2
0
1
1175
0
0
0
0