MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1055

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MCIMX281AVM4B

Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets

Specifications of MCIMX281AVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
13.3.30 DCP Channel 3 Status Register (HW_DCP_CH3STAT)
The DCP Channel 3 Interrupt Status register contains the interrupt status bit and the tag of
the last completed operation from the command chain. If an error occurs during processing,
the ERROR bit is set and an interrupt is generated.
HW_DCP_CH3STAT: 0x1E0
HW_DCP_CH3STAT_SET: 0x1E4
HW_DCP_CH3STAT_CLR: 0x1E8
HW_DCP_CH3STAT_TOG: 0x1EC
The interrupt status register is updated at the end of each work packet. If the interrupt bit
is set in the command packet's command field, an interrupt will be generated once the packet
has completed. In addition, the tag value from the command is stored in the TAG field so
that software can identify which command structure was the last to complete. If an error
occurs, the ERROR bit is set and processing of the command chain is halted.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
W
W
R
R
31
15
0
0
HW_DCP_CH3STAT
30
14
0
0
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
TAG
RSVD0
8002_8000h base + 1E0h offset = 8002_81E0h
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
23
0
0
7
22
0
0
6
21
0
5
0
Chapter 13 Data Co-Processor (DCP)
ERROR_CODE
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
1055
16
0
0
0

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