MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1170
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 1170 of 2327
- Download datasheet (17Mb)
Programmable Registers
14.8.70 DRAM Control Register 75 (HW_DRAM_CTL75)
This is a DRAM configuration register.
Address:
Re-
1170
set
Bit
W
R
PHY_CTRL_
REG_1_0
31
0
Field
31 0
30
0
29
0
HW_DRAM_CTL75
28
0
Controls pad termination and loopback for data slice 0.
There is a separate phy_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus.
Bits [31:28] = Defines the pad dynamic termination select enable time. Larger values add greater delay to
when tsel turns on. Each bit changes the output enable time by a 1/2 cycle resolution.
Bits [27:24] = Defines the pad dynamic termination select disable time. Larger values reduce the delay to
when tsel turns off. Each bit changes the output enable time by a 1/2 cycle resolution.
Bit [23] = Enables dynamic termination select in the PHY for the DQS pads.
'b0 = Disabled
'b1 = Enabled
Bit [22] = Controls the polarity of the tsel signal for the DQS and DM pads.
'b0 = Positive Polarity
'b1 = Negative Polarity
Bit [21] = Triggers a data return to the EMI.
'b0 = No action
'b1 = Sends loopback data on the dfi_rddata signal.
Bit [20] = Selects data output type for phy_obs_reg_0_X [23:8].
'b0 = Return the expected data.
'b1 = Return the actual data.
Bits [19:18] = Loopback control.
'b00 = Normal operational mode.
'b01 = Enables loopback write mode.
'b10 = Stop loopback to check the error register.
'b11 = Clear loopback registers.
Bits [17] = Controls the loopback read multiplexer.
Bits [16] = Controls the internal write multiplexer.
Bits [14:12] = Sets the cycle delay between the LFSR and loopback error check logic. Note that 'h7 is not a
valid selection and will result in a false passing result.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_DRAM_CTL75 field descriptions
800E_0000h base + 12Ch offset = 800E_012Ch
22
0
21
0
20
0
19
0
PHY_CTRL_REG_1_0
18
0
17
0
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0
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