MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 601

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.5.82 AHB to APBX DMA Channel 10 Debug Information
This register gives debug visibility for the APB and AHB byte counts for DMA Channel
10.
This register allows debug visibility of the APBX DMA Channel 10.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
31
0
30
0
Field
29
0
(HW_APBX_CH10_DEBUG2)
HW_APBX_CH10_DEBUG2
28
0
27
0
HW_APBX_CH10_DEBUG1 field descriptions (continued)
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
APB_BYTES
0
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0C
0x0D
0x0E
0x0F
0x15
0x1C
0x1E
24
0
REQ_CMD2 — State in which the DMA is waiting to receive the second word of a command.
XFER_DECODE — The state machine processes the descriptor command field in this state
and branches accordingly.
REQ_WAIT — The state machine waits in this state for the PIO APB cycles to complete.
REQ_CMD4 — State in which the DMA is waiting to receive the fourth word of a command,
or waiting to receive the PIO words when PIO count is greater than 1.
PIO_REQ — This state determines whether another PIO cycle needs to occur before starting
DMA transfers.
READ_FLUSH — During a read transfers, the state machine enters this state waiting for the
last bytes to be pushed out on the APB.
READ_WAIT — When an AHB read request occurs, the state machine waits in this state
for the AHB transfer to complete.
WRITE — During DMA Write transfers, the state machine waits in this state until the AHB
master arbiter accepts the request from this channel.
READ_REQ — During DMA Read transfers, the state machine waits in this state until the
AHB master arbiter accepts the request from this channel.
CHECK_CHAIN — Upon completion of the DMA transfers, this state checks the value of
the Chain bit and branches accordingly.
XFER_COMPLETE — The state machine goes to this state after the DMA transfers are
complete, and determines what step to take next.
WAIT_END — When the Wait for Command End bit is set, the state machine enters this
state until the DMA device indicates that the command is complete.
WRITE_WAIT — During DMA Write transfers, the state machine waits in this state until the
AHB master completes the write to the AHB memory space.
CHECK_WAIT — If the Chain bit is a 0, the state machine enters this state and effectively
halts.
23
0
22
0
21
0
8002_4000h base + 5C0h offset = 8002_45C0h
20
0
19
0
18
0
17
0
Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
16
0
15
0
14
0
Description
13
0
12
0
11
0
10
0
AHB_BYTES
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
601
0
0