MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1328

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

SD/SDIO/MMC Mode
1328
• Data Time-Out Error The SSP TIMEOUT counter is used to detect a time-out
condition during data write or read operations. The time-out counts any time that the
SSP is waiting on a busy DAT bus. For read operations, the DAT line(s) indicate busy
before the card sends the start bit. For write operations, the DAT line(s) may indicate
busy after the block has been sent to the card. If the time-out counter expires before
the DAT line(s) become ready, the SSP stops any DMA requests, sets the
DATA_TIMEOUT status flag, and asserts a CPU IRQ. The ISR should check the status
register to see that a data time-out has occurred. It can then reset the DMA channel and
the SSP to re-try the operation.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 17-11. SD/MMC Block Transfer Flowchart
SD/MMC Block Read
looks at the CMD line for a
When the response is sent
by the MMC card, the SSP
The received data will also
tell the CPU that it is done.
received CRC7. If there is
indicate to the DMA that it
and begins looking at the
will place the response in
be checked for CRC16. If
Write the BLOCK_READ
SSP sends out the MMC
there is a CRC error, the
When the Data is ready,
start bit and the SSP will
After the block has been
command to SDCTRLx.
asserting DMA request.
command sequence, or
DMA sets SSP Run bit.
DAT line for a Start Bit.
The SSP will check the
Block Read Command
command is sent, SSP
an error, it will assert a
receive FIFO and start
CRC7 of the response
the MMC will send the
SSP will assert a CPU
is done. The DMA can
checked, the SSP will
XFER_COUNT=512
After the Block Read
put the data into the
the RESP register.
packet against the
read and the CRC
then issue a new
DMA PIO cycle:
SD/MMC mode
Example
Read Mode
Response.
CPU IRQ.
IRQ.
SD/MMC Block Write
Block Write Command and
SSP will start issuing DMA
looks at the CMD line for a
When the response is sent
by the MMC card, the SSP
requests to fill the transmit
command sequence or tell
Write the BLOCK_WRITE
begins looking at the DAT
received CRC7. If there is
indicate to the DMA that it
will place the response in
longer busy, the SSP will
data. If the card indicates
a CRC error, the SSP will
SSP sends out the MMC
When the Data line is no
transmitted data will also
and transmitted after the
After the block has been
command to SDCTRLx.
have CRC16 calculated
DMA sets SSP Run bit.
line for Busy Condition.
The SSP will check the
start sending data. The
the CPU that it is done.
command is sent, SSP
CRC7 of the response
an error, it will assert a
is done. The DMA can
checked, the SSP will
XFER_COUNT=512
After the Block Write
the RESP register.
assert a CPU IRQ.
packet against the
sent and the CRC
then issue a new
DMA PIO cycle:
SD/MMC mode
Example
Write Mode
Response.
CPU IRQ.
FIFO.
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