MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1272

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programming the BCH/GPMI Interfaces
16.4.1.1 DMA Structure Code Example
The following code sample illustrates the coding for one write transaction involving 4096
bytes of data payload (eight 512-byte blocks) and 10 bytes of auxiliary payload (also referred
to as metadata) to a 4K NAND page sitting on GPMI CS2.
//----------------------------------------------------------------------------
// generic DMA/GPMI/ECC descriptor struct, order sensitive!
//----------------------------------------------------------------------------
typedef struct {
} GENERIC_DESCRIPTOR;
//----------------------------------------------------------------------------
// allocate 10 descriptors for doing a NAND ECC Write
//----------------------------------------------------------------------------
GENERIC_DESCRIPTOR write[10];
//----------------------------------------------------------------------------
// DMA descriptor pointer to handle error conditions from psense checks
//----------------------------------------------------------------------------
unsigned int * dma_error_handler;
//----------------------------------------------------------------------------
// 8 byte NAND command and address buffer
// any alignment is ok, it is read by the GPMI DMA
//
//
//
//
//----------------------------------------------------------------------------
unsigned char nand_cmd_addr_buffer[8];
//----------------------------------------------------------------------------
// 4096 byte payload buffer used for reads or writes
// needs to be word aligned
//----------------------------------------------------------------------------
unsigned int write_payload_buffer[(4096/4)];
//----------------------------------------------------------------------------
// 65 byte meta-data to be written to NAND
// needs to be word aligned
//----------------------------------------------------------------------------
unsigned int write_aux_buffer[65];
//----------------------------------------------------------------------------
// Descriptor 1: issue NAND write setup command (CLE/ALE)
//----------------------------------------------------------------------------
write[0].dma_nxtcmdar = &write[1];
write[0].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT
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// DMA related fields
unsigned int dma_nxtcmdar;
unsigned int dma_cmd;
unsigned int dma_bar;
// GPMI related fields
unsigned int gpmi_ctrl0;
unsigned int gpmi_compare;
unsigned int gpmi_eccctrl;
unsigned int gpmi_ecccount;
unsigned int gpmi_data_ptr;
unsigned int gpmi_aux_ptr;
byte 0 is write setup command
bytes 1-5 is the NAND address
byte 6 is write execute command
byte 7 is status command
BF_APBH_CHn_CMD_WAIT4ENDCMD
BF_APBH_CHn_CMD_NANDLOCK
BF_APBH_CHn_CMD_CMDWORDS
BF_APBH_CHn_CMD_SEMAPHORE
BF_APBH_CHn_CMD_NANDWAIT4READY(0)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
(1)
(1)
(1 + 5)|
(3)
(0)
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// wait for command to finish before
// prevent other DMA channels from
// point to the next descriptor
// 1 byte command, 5 byte address
// send 3 words to the GPMI
//
//
continuing
taking over
Freescale Semiconductor, Inc.