XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 101

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

7.3.3 EEPROM Test Register
M68HC12B Family — Rev. 8.0
MOTOROLA
Read anytime. Write in special modes only (SMODN = 0). These bits are used for
test purposes only. In normal modes, the bits are forced to 0.
EEODD — Odd Row Programming Bit
EEVEN — Even Row Programming Bit
MARG — Program and Erase Voltage Margin Test Enable Bit
EECPD — Charge Pump Disable Bit
EECPRD — Charge Pump Ramp Disable Bit
EECPM — Charge Pump Monitor Enable Bit
Refers to a physical location in the array rather than an odd byte address
Refers to a physical location in the array rather than an even byte address.
This bit is used to evaluate the program/erase voltage margin.
Known to enhance write/erase endurance of EEPROM cells.
Address: $00F2
0 = Odd row bulk programming/erasing is disabled.
1 = Bulk program/erase all odd rows.
0 = Even row bulk programming/erasing is disabled.
1 = Bulk program/erase all even rows.
0 = Normal operation
1 = Program and erase margin test
0 = Charge pump is turned on during program/erase.
1 = Disable charge pump.
0 = Charge pump is turned on progressively during program/erase.
1 = Disable charge pump controlled ramp up.
0 = Normal operation
1 = Output the charge pump voltage on the IRQ/V
Reset:
Read:
Write:
EEODD
Bit 7
0
Figure 7-4. EEPROM Test Register (EETST)
EEVEN
6
0
EEPROM
MARG
5
0
EECPD
4
0
EECPRD
3
0
PP
EEPROM Control Registers
pin.
2
0
0
EECPM
1
0
Data Sheet
EEPROM
Bit 0
0
0
101