XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 145

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XC912BC32CFU8

Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
11.2.13 PWM Special Mode Register
11.2.14 Port P Data Register
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Only in special mode (SMODN = 0)
These bits are available only in special mode and are reset in normal mode.
DISCR — Disable Channel Counter Reset Bit
DISCP — Disable Compare Count Period Bit
DISCAL — Disable Scale Counter Loading Bit
Read: Anytime
Write: Anytime
PWM functions share port P pins 3 to 0 and take precedence over the
general-purpose port when enabled. When configured as input, a read returns the
This bit disables the normal operation of resetting the channel counter when the
channel counter is written.
This bit disables the normal operation of loading scale counters on a write to the
associated scale register.
Address: $0055
Address: $0056
Reset:
Reset:
Read:
Read:
Write:
Write:
PWM
0 = Normal operation
1 = Write to PWM channel counter does not reset channel counter.
0 = Normal operation
1 = In left-aligned output mode, match of the period does not reset the
0 = Normal operation
1 = Write to PWSCAL0 and PWSCAL1 does not load scale counters.
associated PWM counter register.
DISCR
Bit 7
Bit 7
PP7
Figure 11-25. PWM Special Mode Register (PWTST)
0
Pulse-Width Modulator (PWM)
Figure 11-26. Port P Data Register (PORTP)
DISCP
= Unimplemented
PP6
6
0
6
DISCAL
PP5
5
0
5
Unaffected by reset
PP4
4
0
0
4
PWM3
PP3
3
0
0
3
Pulse-Width Modulator (PWM)
PWM2
PWM Register Descriptions
PP2
2
0
0
2
PWM1
PP1
1
0
0
1
Data Sheet
PWM0
Bit 0
Bit 0
PP0
0
0
145

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