XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 142
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XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
(362 pages)
- Current page: 142 of 362
- Download datasheet (5Mb)
Pulse-Width Modulator (PWM)
11.2.10 PWM Channel Period Registers 0–3
Data Sheet
142
counters, where a match in period changes the counter direction. The duty register
changes the state of the output during the period to determine the duty.
When a channel is enabled, the associated PWM counter starts at the count in the
PWCNTx register using the clock selected for that channel.
In special mode, when DISCP = 1 and is configured for left-aligned output, a match
of period does not reset the associated PWM counter.
Read: Anytime
Write: Anytime
The value in the period register determines the period of the associated PWM
channel. If written while the channel is enabled, the new value takes effect when
Address: $004C
Address: $004D
Address: $004E
Address: $004F
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 11-16. PWM Channel Period Register 0 (PWPER0)
Figure 11-17. PWM Channel Period Register 1 (PWPER1)
Figure 11-18. PWM Channel Period Register 2 (PWPER2)
Figure 11-19. PWM Channel Period Register 3 (PWPER3)
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
1
1
1
1
Pulse-Width Modulator (PWM)
Bit 6
Bit 6
Bit 6
Bit 6
6
1
6
1
6
1
6
1
Bit 5
Bit 5
Bit 5
Bit 5
5
1
5
1
5
1
5
1
Bit 4
Bit 4
Bit 4
Bit 4
4
1
4
1
4
1
4
1
Bit 3
Bit 3
Bit 3
Bit 3
3
1
3
1
3
1
3
1
M68HC12B Family — Rev. 8.0
Bit 2
Bit 2
Bit 2
Bit 2
2
1
2
1
2
1
2
1
Bit 1
Bit 1
Bit 1
Bit 1
1
1
1
1
1
1
1
1
MOTOROLA
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
1
1
1
1
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