XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 256

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
15.9.3 BDLC State Vector Register
Data Sheet
256
This register is provided to substantially decrease the CPU overhead associated
with servicing interrupts while under operation of a multiplex protocol. It provides
an index offset that is directly related to the BDLC’s current state, which can be
used with a user-supplied jump table to rapidly enter an interrupt service routine.
This eliminates the need for the user to maintain a duplicate state machine in
software.
I0, I1, I2, I3 — Interrupt Source Bits
These bits indicate the source of the pending interrupt request. Bits are encoded
according to
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR register except when
the BDLC data register needs servicing (RDRF, RXIFR, or TDRE conditions).
RXIFR and RDRF can only be cleared by a read of the BSVR register followed
by a read of BDR. TDRE can either be cleared by a read of the BSVR register
Address: $00F9
Reset:
Read:
Write:
BSVR
$0C
$1C
$00
$04
$08
$10
$14
$18
$20
Byte Data Link Communications (BDLC)
Bit 7
Figure 15-15. BDLC State Vector Register (BSVR)
0
0
Table
I3
0
0
0
0
0
0
0
0
1
= Unimplemented
I2
0
0
0
0
1
1
1
1
0
15-4.
6
0
0
I1
0
0
1
1
0
0
1
1
0
Table 15-4. Interrupt Sources
I0
0
1
0
1
0
1
0
1
0
I3
5
0
BDLC Rx data register
BDLC Tx data register
No interrupts pending
Symbol invalid or out
Cyclical redundancy
Received IFR byte
check (CRC) error
Loss of arbitration
Interrupt Source
Received EOF
empty (TDRE)
full (RDRF)
I2
4
0
(RXIFR)
of range
Wakeup
I1
3
0
M68HC12B Family — Rev. 8.0
I0
2
0
8 (highest)
Priority
(lowest)
0
1
2
3
4
5
6
7
1
0
0
MOTOROLA
Bit 0
0
0