XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 82

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Operating Modes and Resource Mapping
5.4.2 Register Initialization Register
Data Sheet
82
Address: $0011
EBSWAI — External Bus Module Stop in Wait Bit
EME — Emulate Port E Bit
After reset, the 512-byte register block resides at location $0000 but can be
reassigned to any 2-Kbyte boundary within the standard 64-Kbyte address space.
Mapping of internal registers is controlled by five bits in the register initialization
register (INITRG). The register block occupies the first 512 bytes of the 2-Kbyte
block.
Read: Anytime
Write: Once in normal modes; anytime in special modes
REG15–REG11 — Register Position Bits
Reset:
Read:
Write:
configured for expanded wide mode, but normal external accesses operate as
if the bus in narrow mode. In normal expanded narrow mode, internal visibility is
not allowed and IVIS is ignored.
Normal modes: Write once
Special modes: Write anytime except the first time
This bit controls access to the external bus interface when in wait mode. The
module delays before shutting down in wait mode to allow for final bus activity
to complete.
Normal modes: Write anytime
Special modes: Write never
Removing the registers from the map allows the user to emulate the function of
these registers externally. In single-chip mode, port E data register (PORTE)
and port E data direction register (DDRE) are always in the map regardless of
the state of this bit.
Normal modes: Write once
Special modes: Write anytime except the first time
These bits specify the upper five bits of the 16-bit register address.
1 = Internal bus operations visible on external bus
0 = No visibility of internal bus operations on external bus
1 = External bus shut down during wait mode
0 = External bus and registers continue functioning in wait mode.
1 = PORTE and DDRE removed from the memory map (expanded mode)
0 = PORTE and DDRE in the memory map
REG15
Bit 7
0
Figure 5-2. Register Initialization Register (INITRG)
Operating Modes and Resource Mapping
REG14
6
0
REG13
5
0
REG12
4
0
REG11
3
0
M68HC12B Family — Rev. 8.0
2
0
0
1
0
0
MOTOROLA
MMSWAI
Bit 0
0