XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 316

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Development Support
18.3 Background Debug Mode (BDM)
18.3.1 BDM Serial Interface
Data Sheet
316
Program information is fetched a few cycles before it is used by the CPU. To
monitor cycle-by-cycle CPU activity, it is necessary to externally reconstruct what
is happening in the instruction queue. Internally, the MCU only needs to buffer the
data from program fetches. For system debug it is necessary to keep the data and
its associated address in the reconstructed instruction queue. The raw signals
required for reconstruction of the queue are ADDR, DATA, R/W, ECLK, and status
signals IPIPE1 and IPIPE0.
The instruction queue consists of two 16-bit queue stages and a holding latch on
the input of the first stage. To advance the queue means to move the word in the
first stage to the second stage and move the word from either the holding latch or
the data bus input buffer into the first stage. To start even (or odd) instruction
means to execute the opcode in the high-order (or low-order) byte of the second
stage of the instruction queue.
Background debug mode (BDM) is used for system development, in-circuit testing,
field testing, and programming. BDM is implemented in on-chip hardware and
provides a full set of debug options.
Because BDM control logic does not reside in the CPU, BDM hardware commands
can be executed while the CPU is operating normally. The control logic generally
uses CPU dead cycles to execute these commands, but can steal cycles from the
CPU when necessary. Other BDM commands are firmware based and require the
CPU to be in active background mode for execution. While BDM is active, the CPU
executes a firmware program located in a small on-chip ROM that is available in
the standard 64-Kbyte memory map only while BDM is active.
The BDM control logic communicates serially with an external host development
system, via the BKGD pin. This single-wire approach minimizes the number of pins
needed for development support.
The BDM serial interface requires the external controller to generate a falling edge
on the BKGD pin to indicate the start of each bit time. The external controller
provides this falling edge whether data is transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller
or by the MCU. Data is transferred MSB first at 16 E-clock cycles per bit (nominal
speed). The interface times out if 512 E-clock cycles occur between falling edges
from the host. The hardware clears the command register when this timeout
occurs.
Development Support
M68HC12B Family — Rev. 8.0
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