XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 158

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Standard Timer Module (TIM)
12.3.10 Timer Input Capture/Output Compare Registers
Data Sheet
158
C7F–C0F — Input Capture/Output Compare Channel n Flag
Read: Anytime
Write: Used in the clearing mechanism; set bits cause corresponding bits to
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag
register, set the bit to 1.
Any access to TCNT clears TFLG2 register, if the TFFCA bit in TSCR register
is set.
TOF — Timer Overflow Flag
Address: $008F
Address: $0090
Address: $0091
Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is
cleared automatically by a write to the TFLG2 register with bit 7 set. For
additional information, see the TCRE control bit explanation found in
Timer Interrupt Mask
Figure 12-16. Timer Input Capture/Output Compare Register 0 (TC0)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
be cleared
Bit 15
Bit 7
TOF
Bit 7
Bit 7
Bit 7
0
0
0
Figure 12-15. Timer Interrupt Flag 2 (TFLG2)
Standard Timer Module (TIM)
Bit 14
Bit 6
6
0
0
6
0
6
0
Registers.
Bit 13
Bit 5
5
0
0
5
0
5
0
Bit 12
Bit 4
4
0
0
4
0
4
0
Bit 11
Bit 3
3
0
0
3
0
3
0
M68HC12B Family — Rev. 8.0
Bit 10
Bit 2
2
0
0
2
0
2
0
Bit 9
Bit 1
1
0
0
1
0
1
0
MOTOROLA
12.3.8
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
0
0
0
0