XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 254

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
Data Sheet
254
NOTE:
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3)
The extra logic 1 bits are an enhancement to the J1850 protocol which forces a
byte boundary condition fault. This is helpful in preventing noise onto the J1850 bus
from a corrupted message.
If a loss of arbitration occurs when the BDLC attempts to transmit and after the
IFR byte winning arbitration completes transmission, the BDLC again attempts
to transmit the BDR (with no normalization bit). The BDLC continues
transmission attempts until an error is detected on the bus, or TEOD is set, or
the BDLC transmission is successful.
If loss of arbitration occurs in the last bit of the IFR byte, two additional 1 bits are
not sent out because the BDLC attempts to retransmit the byte in the transmit
shift register after the IRF byte winning arbitration completes transmission.
The TMIFR0 bit is used to request the BDLC to transmit the byte in the BDLC
data register (BDR) as the first byte of a multiple byte IFR without CRC.
Response IFR bytes are still subject to J1850 message length maximums (see
15.7.2 J1850 Frame Format
If the TMIFR0 bit is set, the BDLC attempts to transmit the normalization symbol
followed by the byte in the BDR. After the byte in the BDR has been loaded into
the transmit shift register, a TDRE interrupt (see
Register) occurs similar to the main message transmit sequence. The
programmer should then load the next byte of the IFR into the BDR for
transmission. When the last byte of the IFR has been loaded into the BDR, the
programmer should set the TEOD bit in the BCR2. This instructs the BDLC to
transmit an EOD symbol once the byte in the BDR is transmitted, indicating the
end of the IFR portion of the message frame. The BDLC does not append a
CRC when the TMIFR0 is set.
If the programmer attempts to set the TMIFR0 bit after the EOD symbol has
been received from the bus, the TMIFR0 bit remains in the reset state, and no
attempt is made to transmit an IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting, the TMIFR0 bit is
cleared, and no attempt is made to retransmit the byte in the BDR. If loss of
arbitration occurs in the last bit of the IFR byte, two additional 1 bits are sent out.
1 = If set prior to a valid EOD being received with no CRC error, once the
0 = Bit is cleared automatically once the BDLC has successfully transmitted
EOD symbol has been received, the BDLC attempts to transmit the
appropriate normalization bit followed by IFR bytes. The programmer
should set TEOD after the last IFR byte has been written into the BDR.
After TEOD has been set, the last IFR byte to be transmitted is the last
byte which was written into the BDR.
the EOD symbol, by the detection of an error on the multiplex bus or by
a transmitter underrun caused when the programmer does not write
another byte to the BDR after the TDRE interrupt.
Byte Data Link Communications (BDLC)
and
Figure
15-14).
15.9.3 BDLC State Vector
M68HC12B Family — Rev. 8.0
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