XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 288
XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
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msCAN12 Controller
16.12.4 msCAN12 Bus Timing Register 1
Data Sheet
288
SAMP — Sampling Bit
TSEG22–TSEG10 — Time Segment Bits
1. In this case, PHASE_SEG1 must be at least two times quanta.
This bit determines the number of samples of the serial bus to be taken per bit
time. If set, three samples per bit are taken, the regular one (sample point) and
two preceding samples, using a majority rule. For higher bit rates, SAMP should
be cleared, which means that only one sample will be taken per bit.
Time segments within the bit time fix the number of clock cycles per bit time and
the location of the sample point. See
Address: $0103
Reset:
Read:
Write:
0 = One sample per bit
1 = Three samples per bit.
SYNC_SEG
Transmit point
Sample point
Figure 16-19. msCAN12 Bus Timing Register 1 (CBTR1)
SAMP
Bit 7
0
TSEG22
msCAN12 Controller
6
0
Table 16-7. Time Segment Syntax
TSEG21
System expects transitions to occur on the bus
during this period.
A node in transmit mode will transfer a new value to
the CAN bus at this point.
A node in receive mode will sample the bus at this
point. If the three samples per bit option is selected,
then this point marks the position of the third
sample.
5
0
(1)
TSEG20
Figure
4
0
TSEG13
16-8.
3
0
TSEG12
M68HC12B Family — Rev. 8.0
2
0
TSEG11
1
0
MOTOROLA
TSEG10
Bit 0
0
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