XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 298

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XC912BC32CFU8

Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
msCAN12 Controller
Data Sheet
298
NOTE:
AM7–AM0 — Acceptance Mask Bits
The CIDMR0–CIDMR7 registers can be written only if the SFTRES bit in CMCR0
is set.
If a particular bit in this register is cleared, this indicates that the corresponding
bit in the identifier acceptance register must be the same as its identifier bit
before a match will be detected. The message will be accepted if all such bits
match. If a bit is set, it indicates that the state of the corresponding bit in the
identifier acceptance register will not affect whether or not the message is
accepted.
Address: $011C
Address: $011D
Address: $011E
Address: $011F
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
1 = Ignore corresponding acceptance code register bit.
0 = Match corresponding acceptance code register and identifier bits.
AM7
AM7
AM7
AM7
Figure 16-30. Second Bank msCAN12 Identifier Mask
Bit 7
Bit 7
Bit 7
Bit 7
msCAN12 Controller
AM6
AM6
AM6
AM6
6
6
6
6
Registers (CIDMR4–CIDMR7)
AM5
AM5
AM5
AM5
5
5
5
5
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
AM4
AM4
AM4
AM4
4
4
4
4
AM3
AM3
AM3
AM3
3
3
3
3
M68HC12B Family — Rev. 8.0
AM2
AM2
AM2
AM2
2
2
2
2
AM1
AM1
AM1
AM1
1
1
1
1
MOTOROLA
Bit 0
AM0
Bit 0
AM0
Bit 0
AM0
Bit 0
AM0

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