XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 233

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

15.7 BDLC MUX Interface
15.7.1 Rx Digital Filter
15.7.1.1 Operation
M68HC12B Family — Rev. 8.0
MOTOROLA
impedance. This allows the communication path through the analog transceiver to
be tested without interfering with network activity. Using the BDLC analog loopback
mode in conjunction with the analog transceiver’s loopback mode ensures that,
once the off-chip analog transceiver has exited loopback mode, the BDLC does not
begin communicating before a known condition exists on the J1850 bus.
The MUX (multiplex) interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
The receiver section of the BDLC includes a digital low-pass filter to remove narrow
noise pulses from the incoming message. An outline of the digital filter is shown in
Figure
The clock for the digital filter is provided by the MUX interface clock (see f
parameter in
state of the receiver physical interface (BDRxD) signal is sampled. The BDRxD
signal state is used to determine whether the counter should increment or
decrement at the next negative edge of the clock signal.
The counter increments if the input data sample is high but decrements if the input
sample is low. Therefore, the counter progresses either up toward 15 if, on
average, the BDRxD signal remains high or progresses down toward 0 if, on
average, the BDRxD signal remains low.
INTERFACE
INTERFACE
PHYSICAL
RX DATA
(BDRXD)
CLOCK
FROM
MUX
15-3.
Byte Data Link Communications (BDLC)
Table
Figure 15-3. BDLC Rx Digital Filter Block Diagram
D
INPUT
SYNC
15-2). At each positive edge of the clock signal, the current
Q
UP/DOWN
4-BIT UP/DOWN COUNTER
Byte Data Link Communications (BDLC)
OUT
D
LATCH
DATA
Q
BDLC MUX Interface
RX DATA OUT
FILTERED
Data Sheet
BDLC
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