XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 245

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

15.8 BDLC Protocol Handler
15.8.1 Protocol Architecture
M68HC12B Family — Rev. 8.0
MOTOROLA
This method of arbitration works no matter how many bits of priority encoding are
contained in the message.
During arbitration, or even throughout the transmitting message, when an opposite
bit is detected, transmission is stopped immediately unless it occurs on the eighth
bit of a byte. In this case, the BDLC automatically appends up to two extra logic 1
bits and then stops transmitting. These two extra bits are arbitrated normally and
thus do not interfere with another message. The second logic 1 bit is not sent if the
first loses arbitration. If the BDLC has lost arbitration to another valid message,
then the two extra logic 1s do not corrupt the current message. However, if the
BDLC has lost arbitration due to noise on the bus, then the two extra logic 1s
ensure that the current message is detected and ignored as a noise-corrupted
message.
The protocol handler is responsible for framing, arbitration, CRC
generation/checking, and error detection. The protocol handler conforms to SAE
J1850 – Class B Data Communications Network Interface.
The protocol handler contains the state machine, Rx shadow register, Tx shadow
register, Rx shift register, Tx shift register, and loopback multiplexer as shown in
Figure
DLOOP FROM BCR2
LOOPBACK CONTROL
15-11.
Byte Data Link Communications (BDLC)
Figure 15-11. BDLC Protocol Handler Outline
Rx SHADOW REGISTER
Rx SHIFT REGISTER
BDRxD
MULTIPLEXER
LOOPBACK
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
TO PHYSICAL INTERFACE
STATE MACHINE
BDTxD
Byte Data Link Communications (BDLC)
Tx SHADOW REGISTER
Tx SHIFT REGISTER
BDLC Protocol Handler
8
Data Sheet
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