XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 319

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

18.3.2 Enabling BDM Firmware Commands
18.3.3 BDM Commands
M68HC12B Family — Rev. 8.0
MOTOROLA
BDM is available in all operating modes, but must be made active before firmware
commands can be executed. BDM is enabled by setting the ENBDM bit in the BDM
STATUS register via the single-wire interface (using a hardware command;
WRITE_BD_BYTE at $FF01). BDM must then be activated to map BDM registers
and ROM to addresses $FF00 to $FFFF and to put the MCU in active background
mode.
After the firmware is enabled, BDM can be activated by the hardware
BACKGROUND command, by the BDM tagging mechanism, or by the CPU BGND
instruction. An attempt to activate BDM before firmware has been enabled causes
the MCU to resume normal instruction execution after a brief delay.
BDM becomes active at the next instruction boundary following execution of the
BDM BACKGROUND command, but tags activate BDM before a tagged
instruction is executed.
In special single-chip mode, background operation is enabled and active
immediately out of reset. This active case replaces the M68HC11 boot function and
allows programming a system with blank memory.
While BDM is active, a set of BDM control registers is mapped to addresses $FF00
to $FF06. The BDM control logic uses these registers which can be read anytime
by BDM logic, not user programs. Refer to
descriptions.
Some on-chip peripherals have a BDM control bit which allows suspending the
peripheral function during BDM. For example, if the timer control is enabled, the
timer counter is stopped while in BDM. Once normal program flow is continued, the
timer counter is re-enabled to simulate real-time operations.
All BDM command opcodes are eight bits long and can be followed by an address
and/or data, as indicated by the instruction. These commands do not require the
CPU to be in active BDM for execution.
The host controller must wait 150 cycles for a non-intrusive BDM command to
execute before another command can be sent. This delay includes 128 cycles for
the maximum delay for a dead cycle. For data read commands, the host must insert
this delay between sending the address and attempting to read the data.
BDM logic retains control of the internal buses until a read or write is completed. If
an operation can be completed in a single cycle, it does not intrude on normal CPU
operation. However, if an operation requires multiple cycles, CPU clocks are frozen
until the operation is complete.
The two types of BDM commands are:
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Hardware
Firmware
Development Support
18.3.4 BDM Registers
Background Debug Mode (BDM)
Development Support
for detailed
Data Sheet
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