XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 189

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

13.4.12 Pulse Accumulator A Flag Register
M68HC12B Family — Rev. 8.0
MOTOROLA
NOTE:
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 since the E ÷
64 clock is generated by the timer prescaler.
CLK1 and CLK0 — Clock Select Bits
PAOVI — Pulse Accumulator A Overflow Interrupt Enable Bit
PAI — Pulse Accumulator Input Interrupt Enable Bit
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register
will clear all the flags in the PAFLG register.
PAOVF — Pulse Accumulator A Overflow Flag
PAIF — Pulse Accumulator Input Edge Flag
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the
timer is always used as an input clock to the timer counter. The change from one
selected clock to the other happens immediately after these bits are written.
Set when the 16-bit pulse accumulator A overflows from $FFFF to $0000 or
when 8-bit pulse accumulator 3 (PAC3) overflows from $FF to $00. This bit is
cleared automatically by a write to the PAFLG register with bit 1 set.
Set when the selected edge is detected at the PT7 input pin. In event mode, the
event edge triggers PAIF and, in gated time accumulation mode, the trailing
edge of the gate signal at the PT7 input pin triggers PAIF. This bit is cleared by
a write to the PAFLG register with bit 0 set. Any access to the PACN3 and
PACN2 registers will clear all the flags in this register when TFFCA bit in register
TSCR ($86) is set.
Address: $00A1
Reset:
Read:
Write:
0 = Interrupt inhibited
1 = Interrupt requested if PAOVF is set
0 = Interrupt inhibited
1 = Interrupt requested if PAIF is set
Figure 13-30. Pulse Accumulator A Flag Register (PAFLG)
CLK1
0
0
1
1
Bit 7
Enhanced Capture Timer (ECT) Module
0
0
CLK0
0
1
0
1
6
0
0
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65,536 as timer counter clock frequency
5
0
0
4
0
0
Clock Source
Enhanced Capture Timer (ECT) Module
3
0
0
2
0
0
PAOVF
Timer Registers
1
0
Data Sheet
PAIF
Bit 0
0
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