XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 126

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XC912BC32CFU8

Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
Clock Generation Module (CGM)
Data Sheet
126
CME — Clock Monitor Enable Bit
FCME — Force Clock Monitor Enable Bit
FCM — Force Clock Monitor Reset Bit
FCOP — Force COP Watchdog Reset Bit
DISR — Disable Resets from COP Watchdog and Clock Monitor Bit
CR2, CR1, and CR0 — COP Watchdog Timer Rate Select Bit
Write anytime.
If FCME is set, this bit has no meaning or effect.
Write once in normal modes, anytime in special modes.
In normal modes, when this bit is set, the clock monitor function cannot be
disabled until a reset occurs.
To use both STOP and clock monitor, the CME bit should be cleared prior to
executing a STOP instruction and set after recovery from STOP. Always keep
FCME = 0, if STOP will be used.
Writes are not allowed in normal modes, anytime in special modes.
If DISR is set, this bit has no effect.
Writes are not allowed in normal modes; can be written anytime in special
modes.
If DISR is set, this bit has no effect.
Writes are not allowed in normal modes, anytime in special modes.
The COP system is driven by a constant frequency of E/2
RTICTL register allows all but two stages of this divider to be bypassed for
testing in special modes only.) These bits specify an additional division factor to
arrive at the COP timeout rate. The clock used for this module is the E clock.
Write once in normal modes, anytime in special modes.
0 = Clock monitor is disabled; slow clocks and STOP instruction may be
1 = Slow or stopped clocks (including the STOP instruction) cause a clock
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks cause a clock reset sequence.
0 = Normal operation
1 = Force a clock monitor reset, if clock monitor is enabled.
0 = Normal operation
1 = Force a COP reset, if COP is enabled.
0 = Normal operation
1 = Regardless of other control bit states, COP and clock monitor do not
used.
reset sequence.
generate a system reset.
Clock Generation Module (CGM)
M68HC12B Family — Rev. 8.0
13
. (RTBYP in the
MOTOROLA

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