XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 237

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

15.7.2.8 BREAK — Break
15.7.2.9 IDLE — Idle Bus
15.7.3 J1850 VPW Symbols
M68HC12B Family — Rev. 8.0
MOTOROLA
However, if the BDLC is waiting for the IFS period to expire before beginning a
transmission and a rising edge is detected before the IFS time has expired, it
synchronizes internally to that edge.
A rising edge may occur during the IFS period because of varying clock tolerances
and loading of the J1850 bus, causing different nodes to observe the completion of
the IFS period at different times. To allow for individual clock tolerances, receivers
must synchronize to any SOF occurring during an IFS period.
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats the BREAK as
if a transmission error had occurred and halts transmission.
If the BDLC detects a BREAK symbol while receiving a message, it treats the
BREAK as a reception error and sets the invalid symbol flag in the BSVR, also
ignoring the frame it was receiving. If while receiving a message in 4X mode, the
BDLC detects a BREAK symbol, it treats the BREAK as a reception error, sets the
invalid symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2 is
cleared automatically). If bus control is required after the BREAK symbol is
received and the IFS time has elapsed, the programmer must resend the
transmission byte using highest priority.
An idle condition exists on the bus during any passive period after expiration of the
IFS period (for example, > 300 µs). Any node sensing an idle bus condition can
begin transmission immediately.
Huntsinger’s variable pulse-width modulation (VPW) is an encoding technique in
which each bit is defined by the time between successive transitions and by the
level of the bus between transitions (for instance, active or passive). Active and
passive bits are used alternately. This encoding technique is used to reduce the
number of bus transitions for a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either the active
or passive level and one of two lengths, either 64 µs or 128 µs (t
baud rate), depending upon the encoding of the previous bit. The start-of-frame
(SOF), end-of-data (EOD), end-of-frame (EOF), and inter-frame separation (IFS)
symbols are always encoded at an assigned level and length. See
Each message begins with an SOF symbol, an active symbol, and, therefore, each
data byte (including the CRC byte) begins with a passive bit, regardless of whether
it is a logic 1 or a logic 0.
Byte Data Link Communications (BDLC)
Byte Data Link Communications (BDLC)
BDLC MUX Interface
NOM
Figure
at 10.4 Kbps
Data Sheet
15-5.
237