XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 31

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

1.6.3.8 ADDR15–ADDR0 and DATA15–DATA0
1.6.3.9 R/W
1.6.3.10 LSTRB
1.6.3.11 IPIPE1 and IPIPE0
1.6.3.12 DBE
M68HC12B Family — Rev. 8.0
MOTOROLA
ADDR15–ADDR0 and DATA15–DATA0 are the external address and data bus
pins. They share functions with general-purpose I/O ports A and B. In single-chip
operating modes, the pins can be used for I/O; in expanded modes, the pins are
used for the external buses.
In expanded wide mode, ports A and B multiplex 16-bit data and address buses.
The PA7–PA0 pins multiplex ADDR15–ADDR8 and DATA15–DATA8. The
PB7–PB0 pins multiplex ADDR7–ADDR0 and DATA7–DATA0.
In expanded narrow mode, ports A and B are used for the 16-bit address bus. An
8-bit data bus is multiplexed with the most significant half of the address bus on
port A. In this mode, 16-bit data is handled as two back-to-back bus cycles, one for
the high byte followed by one for the low byte. The PA7–PA0 pins multiplex
ADDR15–ADDR8, DATA15–DATA8, and DATA7–DATA0. The state of the
address pin should be latched at the rising edge of E. To allow for maximum
address setup time at external devices, a transparent latch should be used.
R/W is the read/write pin. In all modes, this pin can be used as input/output (I/O)
and is a general-purpose input with an active pullup out of reset. If the read/write
function is required, it should be enabled by setting the RDWE bit in the port E
assignment register (PEAR). External writes are not possible until enabled.
LSTRB is the low-byte strobe pin. In all modes, this pin can be used as I/O and is
a general-purpose input with an active pullup out of reset. If the strobe function is
required, it should be enabled by setting the LSTRE bit in the PEAR register. This
signal is used in write operations and so external low-byte writes are not possible
until this function is enabled. This pin is also used as TAGLO in special expanded
modes and is multiplexed with the LSTRB function.
IPIPE1 and IPIPE0 are the instruction queue tracking pins. Their signals are used
to track the state of the internal instruction execution queue. Execution state is
time-multiplexed on the two signals.
DBE is the data bus enable signal. It is an active-low signal that is asserted low
during E-clock high time. DBE provides separation between output of a multiplexed
address and the input of data. When an external address is stretched, DBE is
asserted during what would be the last quarter cycle of the last E-clock cycle of
stretch. In expanded modes, this pin is used to enable the drive control of external
buses during external reads only. Use of the DBE is controlled by the NDBE bit in
the PEAR register. DBE is enabled out of reset in expanded modes. This pin has
an active pullup during and after reset in single-chip modes.
General Description
Pinout and Signal Descriptions
General Description
Data Sheet
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