XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 161

no-image

XC912BC32CFU8

Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
12.3.11 Pulse Accumulator Control Register
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Anytime for output compare function; has no meaning or effect during
Depending on the TIOS bit for the corresponding channel, these registers are used
to latch the value of the free-running counter when a defined transition is sensed
by the corresponding input capture edge detector or to trigger an output action for
output compare.
Read: Anytime
Write: Anytime
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
Address: $009E
Address: $009F
Address: $00A0
PAEN is independent from TEN.
Figure 12-23. Timer Input Capture/Output Compare Register 7 (TC7)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
0 = Pulse accumulator system disabled
1 = Pulse accumulator system enabled
0 = Event counter mode
1 = Gated time accumulation mode
input capture
Figure 12-24. Pulse Accumulator Control Register (PACTL)
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
Standard Timer Module (TIM)
= Unimplemented
PAEN
Bit 14
Bit 6
6
0
6
0
6
0
PAMOD
Bit 13
Bit 5
5
0
5
0
5
0
PEDGE
Bit 12
Bit 4
4
0
4
0
4
0
Bit 11
CLK1
Bit 3
3
0
3
0
3
0
Standard Timer Module (TIM)
Bit 10
CLK0
Bit 2
2
0
2
0
2
0
PAOVI
Bit 9
Bit 1
1
0
1
0
1
0
Block Diagram
Data Sheet
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
PAI
0
0
0
161

Related parts for XC912BC32CFU8