XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 184

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Enhanced Capture Timer (ECT) Module
Data Sheet
184
PTN
DETECTOR
EDGE
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag
register, set the bit to 1.
TOF — Timer Overflow Flag
When TFFCA bit in TSCR register is set, a read from an input capture or a write
into an output compare channel ($90–$9F) will cause the corresponding
channel flag CnF to be cleared. See
TOF is set when the 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with bit 7 set.
See the explanation of the TCRE control bit in
Registers.)
Address: $008F
Reset:
Read:
Write:
Figure 13-19. C3F–C0F Interrupt Flag Setting
cleared). Any access to TCNT will clear the TFLG2 register, if the TFFCA
bit in the TSCR register is set.
COUNTER
DELAY
Bit 7
TOF
Enhanced Capture Timer (ECT) Module
0
Figure 13-20. Main Timer Interrupt Flag 2 (TFLG2)
6
0
0
TCN INPUT CAPTURE
16-BIT MAIN TIMER
TCNH IC HOLDING
REGISTER
REGISTER
5
0
0
Figure
4
0
0
BUFEN • LATQ • TFMOD
13-19.
3
0
0
13.4.8 Timer Interrupt Mask
M68HC12B Family — Rev. 8.0
2
0
0
1
0
0
MOTOROLA
SET CNF
INTERRUPT
Bit 0
0
0