XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 231

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

15.5.1 BDLC Wait and CPU Wait Mode
15.5.2 BDLC Stop and CPU Wait Mode
M68HC12B Family — Rev. 8.0
MOTOROLA
NOTE:
NOTE:
Depending upon which low-power mode instruction the CPU executes and which
mode the BDLC enters, the message which wakes up the BDLC (and the CPU)
may not be received correctly. Three possibilities are described here. These
descriptions apply regardless of whether the BDLC is in normal or 4X mode when
the STOP or WAIT instruction is executed.
This power-saving mode is entered automatically from run mode when the WCM
bit in BCR1 register is cleared followed by a CPU WAIT instruction. In BDLC wait
mode, the BDLC cannot drive data. A subsequent J1850 network rising edge
wakes up the BDLC.
In this mode, the BDLC internal clocks continue to run as do the MCU clocks. The
first passive-to-active transition on the J1850 network generates a CPU interrupt
request by the BDLC which wakes up the BDLC and CPU. The BDLC correctly
receives the entire message which generated the CPU interrupt request.
Ensure that all transmissions are complete or aborted prior to putting the BDLC into
wait mode (WCM = 0 in BCR1).
This power-conserving mode is entered automatically from run mode when the
WCM bit in the BCR1 register is set followed by a CPU WAIT instruction. This is
the lowest-power mode that the BDLC can enter.
In this mode:
The first passive-to-active transition on the J1850 network generates a
non-maskable ($20) CPU interrupt request by the BDLC, allowing the CPU to
restart the BDLC internal clocks.
To correctly receive future J1850 wakeup traffic, users must read an EOF (end of
frame) in the BSVR prior to placing the BDLC into stop mode (WCM = 1). Then, the
new message which wakes up the BDLC from the BDLC stop mode and the CPU
from the CPU wait mode, is received correctly.
Ensure that all transmissions are complete or aborted prior to putting the BDLC into
stop mode (WCM = 1 in BCR1).
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•
•
The BDLC internal clocks are stopped.
The CPU internal clocks continue to run.
The BDLC awaits J1850 network activity.
Byte Data Link Communications (BDLC)
Byte Data Link Communications (BDLC)
Power-Conserving Modes
Data Sheet
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