XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 165

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

12.3.16 Data Direction Register for Timer Port
12.4 Timer Operation in Modes
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Anytime
The timer forces the I/O state to be an output for each timer port pin associated with
an enabled output compare. In these cases the data direction bits will not be
changed, but they have no affect on the direction of these pins. The DDRT will
revert to controlling the I/O direction of a pin when the associated timer output
compare is disabled. Input captures do not override the DDRT settings.
Stop
BDM
Wait
Normal
TEN = 0
PAEN = 0 — All pulse accumulator operations are stopped.
Address: $00AF
Reset:
Read:
Write:
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
Figure 12-29. Data Direction Register for Timer Port (DDRT)
— Timer is off since both PCLK and ECLK are stopped.
— Timer keeps running, unless TSBCK = 1.
— Counters keep running, unless TSWAI = 1.
— Timer keeps running, unless TEN = 0.
— All timer operations are stopped, registers may be accessed.
DDT7
Bit 7
0
Gated pulse accumulator ÷64 clock is also disabled.
Registers may be accessed.
Standard Timer Module (TIM)
DDT6
6
0
DDT5
5
0
DDT4
4
0
DDT3
3
0
Standard Timer Module (TIM)
DDT2
Timer Operation in Modes
2
0
DDT1
1
0
Data Sheet
DDT0
Bit 0
0
165