XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 178
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XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
(362 pages)
- Current page: 178 of 362
- Download datasheet (5Mb)
Enhanced Capture Timer (ECT) Module
13.4.4 Output Compare 7 Data Register
13.4.5 Timer Count Registers
Data Sheet
178
Read: Anytime
Write: Anytime
OC7D[7:0] Bits
Read: Anytime
Write: Has no meaning or effect in the normal mode; only writable in special
The 16-bit main timer is an up-counter.
A full access for the counter register should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result than
accessing them as a word.
The period of the first count after a write to the TCNT registers may be a different
size because the write is not synchronized with the prescaler clock.
The bits of OC7D correspond bit-for-bit with the bits of the timer port (PORTT).
When a successful OC7 compare occurs, for each bit that is set in OC7M, the
corresponding data bit in OC7D is stored to the corresponding bit of the timer
port.
When the OC7Mn bit is set, a successful OC7 action will override a successful
OC[6:0] compare action during the same cycle; therefore, the OCn action taken
will depend on the corresponding OC7D bit.
Address: $0083
Address: $0084
Address: $0085
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
modes (SMODN = 0)
OC7D7
Bit 15
Figure 13-9. Output Compare 7 Data Register (OC7D)
Bit 7
Bit 7
Bit 7
Bit 7
Enhanced Capture Timer (ECT) Module
0
0
0
Figure 13-10. Timer Count Registers (TCNT)
= Unimplemented
OC7D6
Bit 14
Bit 6
6
0
6
0
6
0
OC7D5
Bit 13
Bit 5
5
0
5
0
5
0
OC7D4
Bit 12
Bit 4
4
0
4
0
4
0
OC7D3
Bit 11
Bit 3
3
0
3
0
3
0
OC7D2
M68HC12B Family — Rev. 8.0
Bit 10
Bit 2
2
0
2
0
2
0
OC7D1
Bit 9
Bit 1
1
0
1
0
1
0
MOTOROLA
OC7D0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
0
0
0
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