XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 230

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
15.4.3 Run Mode
15.5 Power-Conserving Modes
Data Sheet
230
In reset mode, the internal BDLC voltage references are operative, V
to the internal circuits which are held in their reset state, and the internal BDLC
system clock is running. Registers assume their reset condition. Because outputs
are held in their programmed reset state, inputs and network activity are ignored.
This mode is entered from reset mode after all MCU reset sources are no longer
asserted. Run mode is entered from the BDLC wait mode when activity is sensed
on the J1850 bus.
Run mode is entered from the BDLC stop mode when network activity is sensed,
although messages are not received properly until the clocks have stabilized and
the CPU is also in run mode.
In this mode, normal network operation takes place. Ensure that all BDLC
transmissions have ceased before exiting this mode.
The BDLC has three power-conserving modes:
Depending upon the logic level of the WCM bit in BDLC control register 1 (BCR1),
the BDLC enters a power-conserving mode when the CPU executes the STOP or
WAIT instruction.
When a power-conserving mode is entered, any activity on the J1850 network
causes the BDLC to exit low-power mode. When exiting from BDLC stop mode, the
BDLC generates an unmaskable interrupt of the CPU. This wakeup interrupt state
is reflected in the BDLC state vector register (BSVR) and encoded as the highest
priority interrupt.
Wait mode or stop mode does not reset the BDLC registers upon BDLC wakeup.
To disengage a BDLC node from receiving J1850 traffic:
The BDLC can then be put into wait mode or stop mode and does not wake up with
J1850 traffic.
1. BDLC wait and CPU wait mode
2. BDLC stop and CPU wait mode
3. BDLC stop and CPU stop mode
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•
•
Verify all BSVR flags are clear.
Do not load the BDR.
Set the ALOOP bit (after placing the analog transceiver into loopback mode)
or DLOOP bit in BCR2.
Byte Data Link Communications (BDLC)
M68HC12B Family — Rev. 8.0
DD
is supplied
MOTOROLA