XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 109

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

8.4 Operation
8.4.1 Bootstrap Operation Single-Chip Mode
M68HC12B Family — Rev. 8.0
MOTOROLA
LAT — Latch Control Bit
ENPE — Enable Programming/Erase Bit
The FLASH EEPROM can contain program and data. On reset, it can operate as
a bootstrap memory to provide the CPU with internal initialization information
during the reset sequence.
After reset, the CPU controlling the system will begin booting up by fetching the first
program address from address $FFFE.
This bit can be read anytime or written when ENPE = 0. When set, the FLASH
EEPROM is configured for programming or erasure and, upon the next valid
write to the array, the address and data will be latched for the programming
sequence. See
detect circuit on the V
programming voltage is at normal levels.
ENPE can be asserted only after LAT has been asserted and a write to the data
and address latches has occurred. If an attempt is made to assert ENPE when
LAT is negated, or if the latches have not been written to after LAT was
asserted, ENPE will remain negated after the write cycle is complete.
The LAT, ERAS, and BOOTP bits cannot be changed when ENPE is asserted.
A write to FEECTL may affect only the state of ENPE. Attempts to read a FLASH
EEPROM array location in the FLASH EEPROM module while ENPE is
asserted will not return the data addressed. See
FLASH EEPROM module control registers may be read or written while ENPE
is asserted. If ENPE is asserted and LAT is negated on the same write access,
no programming or erasure will be performed.
0 = Programming latches disabled
1 = Programming latches enabled
0 = Disables program/erase voltage to FLASH EEPROM
1 = Applies program/erase voltage to FLASH EEPROM
ENPE
0
0
0
1
Table 8-1. Effects of ENPE, LAT, and ERAS on Array Reads
Table 8-1
LAT
—
0
1
1
FLASH EEPROM
FP
pin will prevent assertion of the LAT bit when the
ERAS
for the effects of LAT on array reads. A high voltage
—
—
0
1
Normal read of location addressed
Read of location being programmed
Normal read of location addressed
Read cycle is ignored
Table 8-1
Result of Read
for more information.
FLASH EEPROM
Data Sheet
Operation
109