XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 65

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

3.3.6 Condition Code Register
3.4 Data Types
M68HC12B Family — Rev. 8.0
MOTOROLA
S — Stop Disable Bit
X — XIRQ Interrupt Mask Bit
H — Half-Carry Flag
I — Interrupt Mask Bit
N — Negative Flag
Z — Zero Flag
V — Two’s Complement Overflow Flag
C — Carry/Borrow Flag
The CPU12 supports four data types:
A byte is eight bits wide and can be accessed at any byte location. A word is
composed of two consecutive bytes with the most significant byte at the lower
value address. There are no special requirements for alignment of instructions or
operands.
1. Bit data
2. 8-bit and 16-bit signed and unsigned integers
3. 16-bit unsigned fractions
4. 16-bit addresses
Setting the S bit disables the STOP instruction.
Setting the X bit masks interrupt requests from the XIRQ pin.
The H flag is used only for BCD arithmetic operations. It is set when an ABA,
ADD, or ADC instruction produces a carry from bit 3 of accumulator A. The DAA
instruction uses the H flag and the C flag to adjust the result to the correct BCD
format.
Setting the I bit disables maskable interrupt sources.
The N flag is set when the result of an operation is less than 0.
The Z flag is set when the result of an operation is all 0s.
The V flag is set when a two’s complement overflow occurs.
The C flag is set when an addition or subtraction operation produces a carry or
borrow.
Reset:
Read:
Write:
U = Unaffected
Bit 7
S
1
Central Processor Unit (CPU)
Figure 3-9. Condition Code Register (CCR)
6
X
1
H
U
5
4
1
I
N
U
3
Central Processor Unit (CPU)
Z
U
2
V
U
1
Data Types
Data Sheet
Bit 0
C
U
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