XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 69

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

4.1 Introduction
4.2 Exception Priority
4.3 Maskable Interrupts
M68HC12B Family — Rev. 8.0
MOTOROLA
Data Sheet — M68HC12B Family
Resets and interrupts are exceptions. Each exception has a 16-bit vector that
points to the memory location of the associated exception-handling routine.
Vectors are stored in the upper 128 bytes of the standard 64-Kbyte address map.
The six highest vector addresses are used for resets and non-maskable interrupt
sources. The remainder of the vectors are used for maskable interrupts, and all
must be initialized to point to the address of the appropriate service routine.
A hardware priority hierarchy determines which reset or interrupt is serviced first
when simultaneous requests are made. Six sources are not maskable. The
remaining sources are maskable, and any one of them can be given priority over
other maskable interrupts.
The priorities of the non-maskable sources are:
Maskable interrupt sources include on-chip peripheral systems and external
interrupt service requests. Interrupts from these sources are recognized when the
global interrupt mask bit (I) in the condition code register (CCR) is cleared. The
default state of the I bit out of reset is 1, but it can be written at any time.
Interrupt sources are prioritized by default but any one maskable interrupt source
may be assigned the highest priority by means of the HPRIO register. The relative
priorities of the other sources remain the same.
1. Power-on reset (POR) or RESET pin
2. Clock monitor reset
3. Computer operating properly (COP) watchdog reset
4. Unimplemented instruction trap
5. Software interrupt instruction (SWI)
6. XIRQ signal if X bit in CCR = 0
Resets and Interrupts
Section 4. Resets and Interrupts
Data Sheet
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