XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 287

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

16.12.3 msCAN12 Bus Timing Register 0
M68HC12B Family — Rev. 8.0
MOTOROLA
NOTE:
SJW1 and SJW0 — Synchronization Jump Width Bits
BRP5–BRP0 — Baud Rate Prescaler Bits
The CBTR0 register can be written only if the SFTRES bit in CMCR0 is set.
The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles by which a bit may be shortened, or lengthened, to achieve
resynchronization on data transitions on the bus (see
These bits determine the time quanta (Tq) clock, which is used to build up the
individual bit timing, according to
Address: $0102
Reset:
Read:
Write:
BRP5
Figure 16-18. msCAN12 Bus Timing Register 0 (CBTR0)
SJW1
SJW1
0
0
0
0
1
:
Bit 7
0
0
0
1
1
BRP4
Table 16-5. Synchronization Jump Width
0
0
0
0
1
:
SJW0
msCAN12 Controller
SJW0
6
0
Table 16-6. Baud Rate Prescaler
0
1
0
1
BRP3
0
0
0
0
1
:
BRP5
5
0
BRP2
0
0
0
0
1
:
Table
Synchronization Jump Width
BRP4
BRP1
4
0
0
0
1
1
1
:
16-6.
Programmer’s Model of Control Registers
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
BRP0
BPR3
0
1
0
1
1
:
3
0
Prescaler Value (P)
BPR2
Table
2
0
64
1
2
3
4
:
msCAN12 Controller
16-5).
BPR1
1
0
Data Sheet
BPR0
Bit 0
0
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