XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 170

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Enhanced Capture Timer (ECT) Module
13.3.1 IC Channels
13.3.1.1 Non-Buffered IC Channels
13.3.1.2 Buffered IC Channels
Data Sheet
170
Four IC channels are the same as on the standard timer with one capture register
which memorizes the timer value captured by an action on the associated input pin.
Four other IC channels, in addition to the capture register, also have one buffer
called holding register. This permits the register to memorize two different timer
values without generation of any interrupt.
Four 8-bit pulse accumulators are associated with the four buffered IC channels.
Each pulse accumulator has a holding register to memorize their value by an action
on its external input. Each pair of pulse accumulators can be used as a 16-bit pulse
accumulator.
The 16-bit modulus down-counter can control the transfer of the IC register’s
contents and the pulse accumulators to the respective holding registers for a given
period, every time the count reaches 0. The modulus down-counter can also be
used as a stand-alone timebase with periodic interrupt capability.
The IC channels are composed of four standard IC registers and four buffered IC
channels.
The main timer value is memorized in the IC register by a valid input pin transition.
This will prevent the captured value to be overwritten until it is read.
There are two modes of operations for the buffered IC channels.
IC Latch Mode (see
•
•
•
•
When enabled (LATQ = 1), the main timer value is memorized in the IC register
by a valid input pin transition. The value of the buffered IC register is latched to
its holding register by the modulus counter for a given period when the count
reaches 0, by a write $0000 to the modulus counter or by a write to ICLAT in the
16-bit modulus down-counter control register (MCCTL).
•
An IC register is empty when it has been read or latched into the holding
register.
A holding register is empty when it has been read.
If the corresponding NOVWx bit of the input control overwrite register
(ICOVW) is cleared, with a new occurrence of a capture, the contents of IC
register are overwritten by the new value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture
register cannot be written unless it is empty.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new
occurrence of a capture, the contents of IC register are overwritten by the
Enhanced Capture Timer (ECT) Module
Figure
13-1):
M68HC12B Family — Rev. 8.0
MOTOROLA