XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 265

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

16.3.2 Receive Structures
M68HC12B Family — Rev. 8.0
MOTOROLA
this is feasible for limited CAN bus speeds, it requires that the central processor
unit (CPU) reacts with short latencies to the transmit interrupt.
A double buffer scheme would decouple the reloading of the transmit buffers from
the actual message being sent and as such reduces the reaction requirements on
the CPU. Problems may arise if the sending of a message would be finished just
while the CPU reloads the second buffer. In that case, no buffer would then be
ready for transmission and the bus would be released.
At least three transmit buffers are required to meet the first requirement under all
circumstances. The msCAN12 has three transmit buffers.
The second requirement calls for some sort of internal priorization which the
msCAN12 implements with the “local priority” concept described here.
The received messages are stored in a 2-stage first-in/first-out (FIFO) input. The
two message buffers are mapped into a single memory area (see
While the background receive buffer (RxBG) is exclusively associated to the
msCAN12, the foreground receive buffer (RxFG) is addressable by the CPU12.
This scheme simplifies the handler software since only one address area is
applicable for the receive process.
Both buffers have 13 bytes for storing the CAN control bits, the identifier (standard
or extended), and the data contents. For details, see
of Message
The receiver full flag (RXF) in the msCAN12 receiver flag register (CRFLG) signals
the status of the foreground receive buffer. When the buffer contains a correctly
received message with matching identifier, this flag is set. See
Receiver Flag
On reception, each message is checked to see if it passes the filter (for details see
16.4 Identifier Acceptance
msCAN12 copies the content of RxBG into RxFG
a receive interrupt to the CPU
received message from RxFG and then reset the RXF flag to acknowledge the
interrupt and to release the foreground buffer. A new message, which can follow
immediately after the IFS field of the CAN frame, is received into RxBG. The
over-writing of the background buffer is independent of the identifier filter function.
1. Only if the RXF flag is not set
2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also.
Storage.
Register.
msCAN12 Controller
Filter) and in parallel is written into RxBG. The
(2)
. The user’s receive handler has to read the
(1)
, sets the RXF flag, and emits
16.11 Programmer’s Model
16.12.5 msCAN12
msCAN12 Controller
Message Storage
Figure
Data Sheet
16-2).
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