XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 79

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

5.2.2.2 Special Expanded Narrow Mode
5.2.2.3 Special Single-Chip Mode
5.2.2.4 Special Peripheral Mode
5.2.3 Background Debug Mode
M68HC12B Family — Rev. 8.0
MOTOROLA
This mode is for emulation of normal expanded narrow mode. External 16-bit data
is handled as two back-to-back bus cycles, one for the high byte followed by one
for the low byte. Internal operations continue to use full 16-bit data paths.
This mode can be used to force the MCU to active BDM mode to allow system
debug through the BKGD pin. The MCU does not fetch the reset vector and
execute application code as it would in other modes. Instead, the active
background mode is in control of CPU execution and BDM firmware waits for
additional serial commands through the BKGD pin. There are no external address
and data buses in this mode. The MCU operates as a stand-alone device and all
program and data space are on-chip. External port pins can be used for
general-purpose I/O.
The CPU is not active in this mode. An external master can control on-chip
peripherals for testing purposes. It is not possible to change to or from this mode
without going through reset. Background debugging should not be used while the
MCU is in special peripheral mode as internal bus conflicts between BDM and the
external master can cause improper operation of both modes.
Background debug mode (BDM) is an auxiliary operating mode that is used for
system development. BDM is implemented in on-chip hardware and provides a full
set of debug operations. Some BDM commands can be executed while the CPU is
operating normally. Other BDM commands are firmware based and require the
BDM firmware to be enabled and active for execution.
In special single-chip mode, BDM is enabled and active immediately out of reset.
BDM is available in all other operating modes, but must be enabled before it can
be activated. BDM should not be used in special peripheral mode because of
potential bus conflicts.
Once enabled, background mode can be made active by a serial command sent
via the BKGD pin or execution of a CPU12 BGND instruction. While background
mode is active, the CPU can interpret special debugging commands, read and
write CPU registers, peripheral registers, and locations in memory.
While BDM is active, the CPU executes code located in a small on-chip ROM
mapped to addresses $FF00 to $FFFF; BDM control registers are accessible at
addresses $FF00 to $FF06. The BDM ROM replaces the regular system vectors
while BDM is active. While BDM is active, the user memory from $FF00 to $FFFF
is not in the map except through serial BDM commands.
Operating Modes and Resource Mapping
Operating Modes and Resource Mapping
Operating Modes
Data Sheet
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