XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 272

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

msCAN12 Controller
16.5.2 Interrupt Vectors
16.6 Protocol Violation Protection
Data Sheet
272
The msCAN12 supports four interrupt vectors as shown in
addresses are dependent on the chip integration and to be defined. The relative
interrupt priority is also integration dependent and to be defined.
The msCAN12 will protect the user from accidentally violating the CAN protocol
through programming errors. The protection logic implements these features:
•
•
•
Wakeup
Error interrupts
Receive
Transmit
The receive and transmit error counters cannot be written or otherwise
manipulated.
All registers which control the configuration of the msCAN12 cannot be
modified while the msCAN12 is online. The SFTRES bit in CMCR0 (see
16.12.1 msCAN12 Module Control Register
these registers:
–
–
–
–
–
The TxCAN pin is forced to recessive if the CPU goes into stop mode.
Function
msCAN12 module control register 1 (CMCR1)
msCAN12 bus timing register 0 and 1 (CBTR0 and CBTR1)
msCAN12 identifier acceptance control register (CIDAC)
msCAN12 identifier acceptance registers (CIDAR0–CIDAR7)
msCAN12 identifier mask registers (CIDMR0–CIDMR7)
Table 16-1. msCAN12 Interrupt Vectors
msCAN12 Controller
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
Source
WUPIF
OVRIF
TXE0
TXE1
TXE2
RXF
0) serves as a lock to protect
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
TXEIE0
TXEIE1
TXEIE2
WUPIE
OVRIE
RXFIE
Local
Mask
M68HC12B Family — Rev. 8.0
Table
16-1. The vector
Global
Mask
I bit
MOTOROLA