XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 228

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XC912BC32CFU8

Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
Byte Data Link Communications (BDLC)
15.3 Functional Description
Data Sheet
228
Figure 15-1
contains the software addressable registers and provides the link between the
CPU and the buffers. The buffers provide storage for data received and data to be
transmitted onto the J1850 bus. The protocol handler is responsible for the
encoding and decoding of data bits and special message symbols during
transmission and reception. The MUX interface provides the link between the
BDLC digital section and the analog physical interface. The wave shaping, driving,
and digitizing of data is performed by the physical interface.
Use of the BDLC module in message networking fully implements the SAE
Standard J1850 Class B Data Communication Network Interface specification.
shows the organization of the BDLC module. The CPU interface
Byte Data Link Communications (BDLC)
Figure 15-1. BDLC Block Diagram
PHYSICAL INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
CPU INTERFACE
TO J1850 BUS
TO CPU
BDLC
M68HC12B Family — Rev. 8.0
MOTOROLA

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