XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 36

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

General Description
1.6.4.6 Port AD
1.6.4.7 Port P
Data Sheet
36
The msCAN data direction register (DDRCAN) determines whether each port CAN
pin PCAN[6:2] is an input or output. Setting a bit in DDRCAN makes the
corresponding pin in port CAN an output; clearing a bit makes the corresponding
pin an input. After reset, port CAN pins PCAN[6:2] are configured as inputs.
When a read to the port CAN is performed, the value read from the most significant
bit (MSB) depends on the MSB, PCAN7, of the port CAN data register, PORTCAN,
and the MSB of DDRCAN: it is 0 if DDRCAN7 = 0 and is PCAN7 if DDRCAN7 = 1.
When the PEUCAN bit in the port CAN control register (PCTLCAN) is set, port CAN
input pins PCAN[6:2] are pulled up internally by an active pullup device.
Setting the RDRCAN bit in register PCTLCAN causes the port CAN outputs
PCAN[6:2} to have reduced drive level. Levels are at normal drive capability after
reset. RDRCAN can be written anytime after reset. Refer to Section 16. msCAN12
Controller.
Port AD provides input to the analog-to-digital subsystem and general-purpose
input. When analog-to-digital functions are not enabled, the port has eight
general-purpose input pins, PAD7–PAD0. The ADPU bit in the ATD control register
2 (ATDCTL2) enables the A/D function.
Port AD pins are inputs; no data direction register is associated with this port.
The port has no resistive input loads and no reduced drive controls. Refer to
Section 17. Analog-to-Digital Converter (ATD).
The four pulse-width modulation channel outputs share general-purpose port P
pins. The PWM function is enabled with the PWM enable register (PWEN).
Enabling PWM pins takes precedence over the general-purpose port. When
pulse-width modulation is not in use, the port pins may be used for general-purpose
I/O.
The port P data direction register (DDRP) determines pin direction of port P when
used for general-purpose I/O. When DDRP bits are set, the corresponding pin is
configured for output. On reset, the DDRP bits are cleared and the corresponding
pin is configured for input.
When the PUPP bit in the PWM control register (PWCTL) register is set, all input
pins are pulled up internally by an active pullup device. Pullups are disabled after
reset.
Setting the RDPP bit in the PWCTL register configures all port P outputs to have
reduced drive levels. Levels are at normal drive capability after reset. The PWCTL
register can be read or written anytime after reset. Refer to
Pulse-Width Modulator
General Description
(PWM).
M68HC12B Family — Rev. 8.0
Section 11.
MOTOROLA