XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 107

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

8.3.3 FLASH EEPROM Module Test Register
M68HC12B Family — Rev. 8.0
MOTOROLA
In normal mode, writes to FEETST control bits have no effect and always read 0.
The FLASH EEPROM module cannot be placed in test mode inadvertently during
normal operation.
FSTE — Stress Test Enable Bit
GADR — Gate/Drain Stress Test Select Bit
HVT — Stress Test High Voltage Status Bit
FENLV — Enable Low Voltage Bit
FDISVFP — Disable Status V
VTCK — V
When the V
not allow writing to the LAT bit; the user cannot erase or program the FLASH
module. The FDISVFP control bit enables writing to the LAT bit regardless of
the voltage on the V
When VTCK is set, the FLASH EEPROM module uses the V
control gate voltage; the sense amp timeout path is disabled. This allows for
indirect measurements of the bit cells’ program and erase threshold. If V
V
If V
ZBRK
Address: $00F6
0 = Disables the gate/drain stress circuitry
1 = Enables the gate/drain stress circuitry
0 = Selects the drain stress circuitry
1 = Selects the gate stress circuitry
0 = High voltage not present during stress test
1 = High voltage present during stress test
0 = Disables low voltage transistor in current reference circuit
1 = Enables low voltage transistor in current reference circuit
0 = Enable the automatic lock mechanism if V
1 = Disable the automatic lock mechanism if V
0 = V
1 = V
Reset:
FP
Read:
Write:
Figure 8-3. FLASH EEPROM Module Test Register (FEETST)
> V
(breakdown voltage), the control gate will equal the V
Control gate voltage = V
T
T
T
ZBRK
Check Test Enable Bit
test disable
test enable
FSTE
Bit 7
FP
0
pin is below normal programming voltage, the FLASH module will
, the control gate will be regulated by this equation:
GADR
FLASH EEPROM
FP
6
0
pin.
FP
HVT
Voltage Lock Bit
5
0
ZBRK
FENLV
+ 0.44 × (V
4
0
FDISVFP
3
0
FP
FP
FP
is low.
− V
is low.
FLASH EEPROM Registers
ZBRK
VTCK
2
0
FP
)
FP
pin to control the
FLASH EEPROM
voltage.
STRE
1
0
Data Sheet
FP
MWPR
Bit 0
0
<
107