XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 240

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
15.7.4 J1850 VPW Valid/Invalid Bits and Symbols
Data Sheet
240
The timing tolerances for receiving data bits and symbols from the J1850 bus have
been defined to allow for variations in oscillator frequencies. In many cases, the
maximum time allowed to define a data bit or symbol is equal to the minimum time
allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol is being
received is equal to a single period of the MUX interface clock (t
separation in these maximum time/minimum time concurrences equals one cycle
of t
This one clock resolution allows the BDLC to differentiate properly between the
different bits and symbols. This is done without reducing the valid window for
receiving bits and symbols from transmitters onto the J1850 bus, which has varying
oscillator frequencies.
In Huntsinger’s variable pulse width (VPW) modulation bit encoding, the tolerances
for both the passive and active data bits received and the symbols received are
defined with no gaps between definitions. For example, the maximum length of a
passive logic 0 is equal to the minimum length of a passive logic 1, and the
maximum length of an active logic 0 is equal to the minimum length of a valid SOF
symbol.
See
BDLC
Figure
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
ACTIVE
PASSIVE
.
Figure 15-6. J1850 VPW Received Passive Symbol Times
15-6,
Byte Data Link Communications (BDLC)
Figure
64 µs
A
A
128 µs
15-7, and
200 µs
B
B
Figure
15-8.
C
C
M68HC12B Family — Rev. 8.0
D
(1) INVALID PASSIVE BIT
(2) VALID PASSIVE LOGIC 0
(3) VALID PASSIVE LOGIC 1
(4) VALID EOD SYMBOL
BDLC
), an apparent
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