XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 141
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XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
(362 pages)
- Current page: 141 of 362
- Download datasheet (5Mb)
11.2.9 PWM Channel Counters 0–3
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Anytime
A write causes the PWM counter to reset to $00.
In special mode, if DISCR = 1, a write does not reset the PWM counter.
Each counter may be read anytime without affecting the count or the operation of
the corresponding PWM channel. Writes to a counter cause the counter to be reset
to $00 and force an immediate load of both duty and period registers with new
values. To avoid a truncated PWM period, write to a counter while the counter is
disabled. In left-aligned output mode, resetting the counter and starting the
waveform output is controlled by a match between the period register and the value
in the counter. In center-aligned output mode, the counters operate as up/down
Address: $0048
Address: $0049
Address: $004A
Address: $004B
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
Figure 11-12. PWM Channel Counter 0 (PWCNT0)
Figure 11-13. PWM Channel Counter 1 (PWCNT1)
Figure 11-14. PWM Channel Counter 2 (PWCNT2)
Figure 11-15. PWM Channel Counter 3 (PWCNT3)
Pulse-Width Modulator (PWM)
Bit 6
Bit 6
Bit 6
Bit 6
6
0
6
0
6
0
6
0
Bit 5
Bit 5
Bit 5
Bit 5
5
0
5
0
5
0
5
0
Bit 4
Bit 4
Bit 4
Bit 4
4
0
4
0
4
0
4
0
Bit 3
Bit 3
Bit 3
Bit 3
3
0
3
0
3
0
3
0
Pulse-Width Modulator (PWM)
PWM Register Descriptions
Bit 2
Bit 2
Bit 2
Bit 2
2
0
2
0
2
0
2
0
Bit 1
Bit 1
Bit 1
Bit 1
1
0
1
0
1
0
1
0
Data Sheet
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
141
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