XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 120

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Clock Generation Module (CGM)
10.3 Register Map
10.4 Clock Selection and Generation
Data Sheet
120
$0014
$0015
$0016
$0017
$00E0
Addr.
Real-Time Interrupt Flag Register
COP Control Register (COPCTL)
Slow Mode Divider Register
Real-Time Interrupt Control
Register Name
Arm/Reset COP Timer
Register (COPRST)
Register (RTICTL)
See page 124.
See page 125.
See page 125.
See page 127.
See page 123.
The CGM generates the P clock, the E clock, and four T clocks. The P clock and E
clock are used by all device modules except the CPU. The T clocks are used by
the CPU.
Figure 10-3
There are two types of P clocks and E clocks while in wait mode:
Figure 10-4
(RTIFLG)
(SLOW)
•
•
Global type (G), which is driven by the slow clock divider in wait mode and
drives all on-chip peripherals except the BDLC and the TIMER
Global type (GBT), which remains at the oscillator divide-by-2 rate in wait
mode and drives the BDLC and the TIMER
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
shows clock timing relationships while in normal run modes.
shows clock timing relationships while in wait mode.
Figure 10-2. CGM Register Map
Clock Generation Module (CGM)
Bit 7
RTIE
RTIF
CME
Bit 7
0
0
0
0
0
0
= Unimplemented
RSWAI
FCME
Bit 6
6
0
0
0
0
0
0
0
RSBCK
FCM
Bit 5
5
0
0
0
0
0
0
0
FCOP
Bit 4
4
0
0
0
0
0
0
0
0
RTBYP
DISR
Bit 3
3
0
0
0
0
0
0
0
M68HC12B Family — Rev. 8.0
SLDV2
RTR2
CR2
Bit 2
2
0
0
0
0
0
0
SLDV1
RTR1
CR1
Bit 1
1
0
0
0
0
0
0
MOTOROLA
SLDV0
RTR0
Bit 0
CR0
Bit 0
0
0
0
1
0
0