XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 153
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XC912BC32CFU8
Manufacturer Part Number
XC912BC32CFU8
Description
M68HC12B Family Data Sheet
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC912BC32CFU8.pdf
(362 pages)
- Current page: 153 of 362
- Download datasheet (5Mb)
12.3.5 Timer Count Register
12.3.6 Timer System Control Register
M68HC12B Family — Rev. 8.0
MOTOROLA
Read: Anytime
Write: Has no meaning or effect in normal mode; only writable in special modes
A full access for the counter register should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result than
accessing them as a word.
The period of the first count after a write to the TCNT registers may be a different
size because the write is not synchronized with the prescaler clock.
Read: Anytime
Write: Anytime
TEN — Timer Enable Bit
Address: $0084
Address: $0085
Address: $0086
If for any reason the timer is not active, there is no ÷64 clock for the pulse
accumulator since the E ÷ 64 is generated by the timer prescaler.
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
0 = Disables timer, including the counter; can be used for reducing power
1 = Allows timer to function normally
consumption
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
TEN
Figure 12-7. Timer System Control Register (TSCR)
0
0
0
Standard Timer Module (TIM)
Figure 12-6. Timer Count Register (TCNT)
= Unimplemented
= Unimplemented
TSWAI
Bit 14
Bit 6
6
0
6
0
6
0
TSBCK
Bit 13
Bit 5
5
0
5
0
5
0
TFFCA
Bit 12
Bit 4
4
0
4
0
4
0
Bit 11
Bit 3
3
0
3
0
3
0
0
Standard Timer Module (TIM)
Bit 10
Bit 2
2
0
2
0
2
0
0
Bit 9
Bit 1
1
0
1
0
1
0
0
Block Diagram
Data Sheet
Bit 0
Bit 8
Bit 0
Bit 0
Bit 0
0
0
0
0
153
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