XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 57

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

M68HC12B Family — Rev. 8.0
MOTOROLA
Notes:
Addr.
$00FA
$00FB
$00FC
$00FD
$00FE
$00FF
$0100
$0101
$0102
$0103
$0104
$0105
1. Available only on MC68HC912B32 and MC68HC912BC32 devices.
2. Available only on MC68HC912B32 and MC68HC12BE32 devices.
3. Available only on MC68HC(9)12BC32 devices.
Port DLC Data Direction Register
BDLC Analog Roundtrip Delay
msCAN12 Receiver Interrupt
Enable Register (CRIER)
Register Name
Port DLC Control Register
msCAN12 Module Control
msCAN12 Module Control
BDLC Control Register 2
msCAN12 Receiver Flag
Port DLC Data Register
Register 0 (CMCR0)
Register 1 (CMCR1)
msCAN12 Bus Timing
msCAN12 Bus Timing
Register 0 (CBTR0)
Register 1 (CBTR1)
BDLC Data Register
Register (CRFLG)
Register (BARD)
See page 250.
See page 258.
See page 259.
See page 260.
See page 261.
See page 262.
See page 284.
See page 286.
See page 287.
See page 288.
See page 289.
See page 291.
(PORTDLC)
(DDRDLC)
(DLCSCR)
(BCR2)
(BDR)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
(3)
(3)
(3)
(3)
Figure 2-1. Register Map (Sheet 16 of 19)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
ALOOP
WUPIF
WUPIE
SAMP
SJW1
Bit 7
BD7
ATE
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Register Block
RWRNIF
RWRNIE
TSEG22
DDDLC6
DLOOP
RXPOL
SJW0
BD6
Bit 6
U
6
1
1
0
0
0
0
0
0
0
0
0
0
0
TWRNIF
TWRNIE
TSEG21
DDDLC5
CSWAI
RX4XE
BRP5
BD5
Bit 5
U
5
0
0
0
0
0
0
1
0
0
0
0
0
0
Indeterminate after reset
TSEG20
RERRIE
DDDLC4
RERRIF
SYNCH
BRP4
NBFS
BD4
Bit 4
U
R
4
0
0
0
0
0
0
0
0
0
0
0
0
0
= Reserved
DDDLC3
TLNKEN
TSEG13
TERRIF
TERRIE
TEOD
BPR3
BD3
BO3
Bit 3
U
3
0
0
0
0
0
0
0
0
0
0
0
0
BDLCEN
DDDLC2
TSEG12
BOFFIE
BOFFIF
LOOPB
SLPAK
TSIFR
BPR2
BD2
BO2
Bit 2
U
2
0
1
0
0
0
0
0
0
0
0
U = Unaffected
PUPDLC
DDDLC1
TSEG11
TMIFR1
SLPRQ
WUPM
OVRIF
OVRIE
BPR1
BO1
Bit 1
BD1
Register Block
U
1
0
1
0
0
0
0
0
0
0
0
Data Sheet
Registers
RDPDLC
DDDLC0
CLKSRC
SFTRES
TSEG10
TMIFR0
RXFIE
BPR0
Bit 0
BO0
Bit 0
RXF
BD0
U
0
1
0
0
1
0
0
0
0
0
57