XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 221

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

14.3.5.5 SPI Data Register
14.4 Port S
14.4.1 Port S Data Register
M68HC12B Family — Rev. 8.0
MOTOROLA
NOTE:
Read: Anytime; normally, only after SPIF flag set
Write: Anytime; see WCOL write collision flag in
This 8-bit register is both the input and output register for SPI data. Reads of this
register are double buffered but writes cause data to bewritten directly into the
serial shifter. In the SPI system, the 8-bit data register in the master and the 8-bit
data register in the slave are linked by the MOSI and MISO wires to form a
distributed 16-bit register. When a data transfer operation is performed, this 16-bit
register is serially shifted eight bit positions by the SCK clock from the master so
the data is exchanged effectively between the master and the slave.
Some slave devices are simple and either accept data from the master without
returning data to the master or pass data to the master without requiring data from
the master.
In all modes, port S bits PS7–PS0 can be used for either general-purpose I/O or
with the SCI and SPI subsystems. During reset, port S pins are configured as
high-impedance inputs (DDRS is cleared).
Read: Anytime; inputs return pin level; outputs return pin driver input level
Write: Data stored in internal latch; drives pins only if configured for output; does
Port S shares function with the on-chip serial systems, SPI0 and SCI0.
Pin Function
Address:
Address:
Reset:
Reset:
Read:
Write:
Read:
Write:
not change pin state when pin configured for SPI or SCI output
$00D5
$00D6
Bit 7
Bit 7
Bit 7
PS7
SS
CS
Figure 14-20. Port S Data Register (PORTS)
Figure 14-19. SPI Data Register (SP0DR)
Bit 6
SCK
PS6
6
6
Serial Interface
After reset all bits configured as general-purpose inputs
MOMI
MOSI
Bit 5
PS5
5
5
Unaffected by reset
MISO
SISO
Bit 4
PS4
4
4
Bit 3
PS3
14.3.5.4 SPI Status Register
—
3
3
Bit 2
PS2
—
2
2
TXD0
Bit 1
PS1
Serial Interface
1
1
Data Sheet
RXD0
Bit 0
Bit 0
Bit 0
PS0
Port S
221