XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 183

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

13.4.9 Main Timer Interrupt Flag Registers
M68HC12B Family — Rev. 8.0
MOTOROLA
NOTE:
If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously.
If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is reset from
$FFFF to $0000.
PR2, PR1, and PR0 — Timer Prescaler Select Bits
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be
C7F–C0F — Input Capture/Output Compare Channel n Flag
These three bits specify the number of ÷2 stages that are to be inserted between
the module clock and the main timer counter. See
selected prescale factor will not take effect until the next synchronized edge
where all prescale counter stages equal 0.
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the
flag register, write a 1 to the bit.
Use of the TFMOD bit in the input control system control register (ICSYS)
register ($AB) in conjunction with the use of the ICOVW register ($AA) allows a
timer interrupt to be generated after capturing two values in the capture and
holding registers instead of generating an interrupt for every capture.
Address: $008E
Reset:
Read:
Write:
cleared). Writing a 0 will not affect current bit status.
Value
0
1
2
3
4
5
6
7
Bit 7
C7F
Enhanced Capture Timer (ECT) Module
0
Figure 13-18. Main Timer Interrupt Flag 1 (TFLG1)
PR2
0
0
0
0
1
1
1
1
C6F
6
0
Table 13-3. Prescaler Selection
PR1
0
0
1
1
0
0
1
1
C5F
5
0
PR0
C4F
0
1
0
1
0
1
0
1
4
0
Enhanced Capture Timer (ECT) Module
C3F
3
0
Prescale Factor
Table
C2F
2
0
16
32
32
32
1
2
4
8
13-3. The newly
C1F
Timer Registers
1
0
Data Sheet
Bit 0
C0F
0
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