XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 122

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Clock Generation Module (CGM)
10.5 Slow Mode Divider
10.6 Clock Functions
10.6.1 Computer Operating Properly (COP)
10.6.2 Real-Time Interrupt
10.6.3 Clock Monitor
Data Sheet
122
NOTE:
The slow mode divider is included to deliver a variable bus frequency to the MCU
in wait mode. The bus clocks are derived from the constant P clock. The slow clock
counter divides the P clock and E clock frequency in powers of 2, up to 128. When
the slow control register is cleared or the part is not in wait mode, the slow mode
divider is off and the bus clock’s frequency is not changed.
The clock monitor is clocked by the system clock (oscillator) reference; the slow
mode divider allows operation of the MCU at clock periods longer than the clock
monitor trigger time.
The CGM generates and controls the timing of the reset and POR logic.
The computer operating properly (COP) or watchdog timer is an added check that
a program is running and sequencing properly. When the COP is being used,
software is responsible for keeping a free-running watchdog timer from timing out.
If the watchdog timer times out, it is an indication that the software is no longer
being executed in the intended sequence; thus, a system reset is initiated. Three
control bits allow selection of seven COP timeout periods or COP disable. When
COP is enabled, sometime during the selected period the program must write $55
and $AA (in this order) to the arm/reset COP register (COPRST). If the program
fails to do this, the part resets. If any value other than $55 or $AA is written to
COPRST, the part is reset.
There is a real-time (periodic) interrupt available to the user. This interrupt occurs
at one of seven selected rates. An interrupt flag and an interrupt enable bit are
associated with this function. There are three bits for the rate select.
The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay.
If no MCU clock edges are detected within this RC time delay, the clock monitor
can optionally generate a system reset. The clock monitor function is
enabled/disabled by the CME control bit in the COP control register (COPCTL).
This timeout is based on an RC delay so that the clock monitor can operate without
any MCU clocks.
Clock monitor timeouts are shown in
Clock Generation Module (CGM)
5 V ± 10%
Table 10-1. Clock Monitor Timeout
Supply
Table
10-1.
2–20 µs
Range
M68HC12B Family — Rev. 8.0
MOTOROLA