XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 286

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

msCAN12 Controller
16.12.2 msCAN12 Module Control Register1
Data Sheet
286
NOTE:
NOTE:
LOOPB — Loop Back Self-Test Mode Bit
The ACK bit is added to the CAN frame by the protocol. For more information on
the CAN frame and the ACK bit, refer to the Bosch CAN 2.0 specification.
WUPM — Wakeup Mode Flag
CLKSRC — msCAN12 Clock Source Flag
The CMCR1 register can be written only if the SFTRES bit in CMCR0 is set.
When this bit is set, the msCAN12 performs an internal loop back which can be
used for self-test operation. The bit stream output of the transmitter is fed back
to the receiver. The RxCAN input pin is ignored and the TxCAN output goes to
the recessive state (1). In this state the msCAN12 ignores the bit sent during the
ACK slot of the CAN frame acknowledge field to ensure proper reception of its
own message. Both transmit and receive interrupts are generated.
This flag defines whether the integrated low-pass filter is applied to protect the
msCAN12 from spurious wakeups. See
Function.
This flag defines which clock source the msCAN12 module is driven from (only
for system with CGM module. See
Address: $0101
Reset:
Read:
Write:
0 = Normal operation
1 = Activate loop back self-test mode
0 = msCAN12 will wake up the CPU after any recessive-to- dominant edge
1 = msCAN12 will wake up the CPU only in the case of a dominant pulse on
0 = msCAN12 clock source is EXTALi.
1 = msCAN12 clock source is twice the frequency of ECLK.
Figure 16-17. msCAN12 Module Control Register 1 (CMCR1)
on the CAN bus.
the bus which has a length of approximately t
Bit 7
0
0
= Unimplemented
msCAN12 Controller
6
0
0
5
0
0
16.9 Clock System
4
0
0
16.7.4 Programmable Wakeup
3
0
0
WUP
LOOPB
M68HC12B Family — Rev. 8.0
and
2
0
.
Figure
WUPM
1
0
16-7.
MOTOROLA
CLKSRC
Bit 0
0