XC912BC32CFU8 Motorola Semiconductor Products, XC912BC32CFU8 Datasheet - Page 234

• Manufacturer Part Number: XC912BC32CFU8
• Description: M68HC12B Family Data Sheet
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Communications (BDLC)
15.7.1.2 Performance
Data Sheet
234
When the counter eventually reaches the value 15, the digital filter decides that the
condition of the BDRxD signal is at a stable logic level 1 and the data latch is set,
causing the filtered Rx data signal to become a logic level 1. Furthermore, the
counter is prevented from overflowing and can be decremented only from this
state.
Alternatively, should the counter eventually reach the value 0, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level 0 and the
data latch is reset, causing the filtered Rx data signal to become a logic level 0.
Furthermore, the counter is prevented from underflowing and can be incremented
only from this state.
The data latch retains its value until the counter next reaches the opposite end
point, signifying a definite transition of the signal.
The performance of the digital filter is best described in the time domain rather than
the frequency domain.
If the signal on the BDRxD signal transitions, there is a delay before that transition
appears at the filtered Rx data output signal. This delay is between 15 and 16 clock
periods, depending on where the transition occurs with respect to the sampling
points. This filter delay must be taken into account when performing message
arbitration.
For example, if the frequency of the MUX interface clock (f
then the period (t
noise is 15.259 µs.
The effect of random noise on the BDRxD signal depends on the characteristics of
the noise itself. Narrow noise pulses on the BDRxD signal is ignored completely if
they are shorter than the filter delay. This provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition can be
delayed by an amount equal to the length of the noise burst. This is a reflection of
the uncertainty of where the transition is actually occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the shortest
allowable symbol length, are detected by the next stage of the BDLC’s receiver as
an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length are
detected normally as an invalid symbol or as invalid data when the frame’s CRC is
checked.
Byte Data Link Communications (BDLC)
BDLC
) is 954 ns and the maximum filter delay in the absence of
M68HC12B Family — Rev. 8.0
BDLC
) is 1.0486 MHz,
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